By Asep Darmawan 
A research team from TU Darmstadt has introduced a fundamental shift in how embedded processors defend against side-channel attacks. In a newly released paper, investigators Niels Wieser, Nicolai Müller, and Amir Moradi outline a hardware-level methodology designed to eliminate micro-architectural leakages directly at their source, bypassing the performance penalties traditionally imposed by software-based mitigations.
The study, titled "Hardware-Level Mitigation of Micro-Architectural Leakages in Embedded Processors" (Paper 2026/2478), addresses a longstanding friction point in modern cybersecurity: the delicate balance between cryptographic flexibility, processing performance, and hardware security.
The Cryptographic Dilemma: Flexibility Versus Performance
Cryptographic software has become a cornerstone of modern digital infrastructure. Because security requirements evolve rapidly—driven by the discovery of new vulnerabilities, shifting cryptographic standards, and the emergence of post-quantum algorithms—developers rely heavily on software implementations. Software provides the necessary adaptability to patch, update, and modify cryptographic routines quickly.
However, this flexibility comes at a cost. Dedicated hardware accelerators generally offer superior performance and energy efficiency compared to flexible software implementations running on general-purpose processors. Yet, running cryptography in software on physical hardware introduces a major vulnerability: Side-Channel Analysis (SCA).
Side-channel attacks do not target mathematical flaws in cryptographic algorithms. Instead, they exploit physical manifestations of a device’s operation, such as power consumption, electromagnetic emissions, timing variations, and acoustic signals. By measuring these physical characteristics while a processor handles secret keys, adversaries can deduce sensitive data without ever breaking the underlying encryption math.
The Limits of Masking and Software Countermeasures
To protect cryptographic software against side-channel analysis, cryptographers widely rely on a countermeasure known as masking. In theory, masking offers provable security guarantees by splitting sensitive data into multiple random shares, ensuring that no single intermediate value processed by the hardware reveals information about the secret.
In practice, however, the effectiveness of software-based masking is frequently undermined by the complex realities of modern processor micro-architectures. Pipeline stages, data forwarding, caches, and internal buffer structures can unintentionally combine or manipulate these masked shares, creating unintended micro-architectural leakages.
To account for these hardware-induced vulnerabilities, researchers have developed formal adversary models. These models attempt to predict and simulate micro-architectural leakage under generic assumptions about the underlying hardware. Because these generic assumptions must be conservative to account for wide variations in processor design, they create a demanding environment for software developers and compilers.
To achieve security under such generic models, compilers are forced to generate less performant software. They must insert redundant operations, memory barriers, or artificial delays to prevent the micro-architecture from leaking secret-dependent data. This significantly degrades the performance of the embedded processor.
To bridge this gap, previous research explored secure hardware-software co-design. This approach relies on a precisely specified hardware leakage behavior, which allows compilers to generate more targeted constraints. While this method reduces the performance overhead required to counteract side-channel effects, it does not entirely remove it. Software developers are still burdened with complex, security-aware compilation processes and hardware-specific workarounds.
A Paradigm Shift: Eliminating Leakage at the Register-Transfer Level
Rather than attempting to manage or mask leakage through software constraints and complex compilation rules, the TU Darmstadt research team pursued a more fundamental paradigm: eliminating leakage entirely at its source.
Conceptually, the authors propose architectural modifications to general-purpose processors at the Register-Transfer Level (RTL). By altering the fundamental design of the hardware logic, these modifications remove the root causes of micro-architectural leakages.
Applying these proposed architectural changes enables the secure execution of standard masked software without introducing micro-architectural leakage under the Robust but Relaxed (RR) $d$-probing model. By tackling the problem at the hardware level, the approach removes the need for complex, security-aware compilers and eliminates the requirement for hardware-specific workarounds within the application software.
Implementation and Formal Verification on the Ibex Processor
While the proposed countermeasures are versatile enough to be applied to a wide variety of processor micro-architectures, the researchers validated their approach using a concrete, open-source hardware platform.
The team integrated their proposed architectural changes into the Ibex processor, a widely used open-source 32-bit RISC-V embedded core. To ensure rigorous validation, the security of each countermeasure was formally proven on an individual basis. Furthermore, the researchers evaluated the security of the modified Ibex processor as a complete system.
This evaluation combined tool-assisted leakage assessment of the full netlist with physical experiments conducted on a Field Programmable Gate Array (FPGA). By moving from theoretical modeling to physical implementation and measurement, the study demonstrates that hardware-level architectural modifications can successfully secure embedded processors against sophisticated side-channel attacks without sacrificing operational efficiency or shifting the burden entirely onto software developers.
Lina Hope 
Sagoh 
Neng Nana